#if defined(ARCTIC)
#include "sal.h"
#include "usw/include/drv_enum.h"
#include "usw/include/drv_common.h"

#include "ctc_error.h"

#include "sys_usw_common.h"
#include "sys_usw_interrupt.h"
#include "sys_usw_port_api.h"
#include "../sys_usw_interrupt_priv.h"

enum sys_at_interrupt_type_e
{
    SYS_AT_INTR_CHIP_FATAL = 0,
    SYS_AT_INTR_CHIP_NORMAL = 1,
    SYS_AT_INTR_CPU_SUB_DECODE_0 = 2,
    SYS_AT_INTR_CPU_SUB_DECODE_1 = 3,
    SYS_AT_INTR_CPU_SUB_DECODE_2 = 4,
    SYS_AT_INTR_CPU_SUB_DECODE_3 = 5,
    SYS_AT_INTR_CPU_SUB_ECPU_00 = 6,
    SYS_AT_INTR_CPU_SUB_ECPU_01 = 7,
    SYS_AT_INTR_CPU_SUB_ECPU_10 = 8,
    SYS_AT_INTR_CPU_SUB_ECPU_11 = 9,
    SYS_AT_INTR_CPU_SUB_DMA = 10,
    SYS_AT_INTR_CPU_SUB_UART = 11,
    SYS_AT_INTR_CPU_SUB_QSPI = 12,
    SYS_AT_INTR_CPU_SUB_GPIO = 13,
    SYS_AT_INTR_FUNC_MAC_EVENT = 14,
    SYS_AT_INTR_FUNC_CPU_MAC = 15,
    SYS_AT_INTR_FUNC_BSR_ERM_MON = 16,
    SYS_AT_INTR_FUNC_BSR_IRM_MON = 17,
    SYS_AT_INTR_FUNC_OAM_DEFECT_CACHE = 18,
    SYS_AT_INTR_FUNC_OAM_AUTO_GEN = 19,
    SYS_AT_INTR_FUNC_OAM_TWAMP = 20,
    SYS_AT_INTR_FUNC_FIB_ACC_LEARN_OUT_FIFO =21,
    SYS_AT_INTR_FUNC_MISC_EVENT = 22,
    SYS_AT_INTR_FUNC_MACSEC = 27,
    SYS_AT_INTR_FUNC_PCIE_BURST_DONE = 28,
    SYS_AT_INTR_FUNC_STATS_STATUS_ADDR_SLICE_0 = 29,
    SYS_AT_INTR_FUNC_STATS_STATUS_ADDR_SLICE_1 = 30,
    SYS_AT_INTR_FUNC_STATS_STATUS_ADDR_SLICE_2 = 31,
    SYS_AT_INTR_FUNC_STATS_STATUS_ADDR_SLICE_3 = 32,
    SYS_AT_INTR_FUNC_IPFIX_USEAGE_OVERFLOW = 33,
    SYS_AT_INTR_FUNC_EPE_IPFIX_USEAGE_OVERFLOW = 34,
    SYS_AT_INTR_FUNC_STMCTL_STATE_SLICE_0 = 35,
    SYS_AT_INTR_FUNC_STMCTL_STATE_SLICE_1 = 36,
    SYS_AT_INTR_FUNC_STMCTL_STATE_SLICE_2 = 37,
    SYS_AT_INTR_FUNC_STMCTL_STATE_SLICE_3 = 38,
    SYS_AT_INTR_FUNC_SVC_POLICING_STATUS_ADDR_SLICE_0 = 39,
    SYS_AT_INTR_FUNC_SVC_POLICING_STATUS_ADDR_SLICE_1 = 40,
    SYS_AT_INTR_FUNC_SVC_POLICING_STATUS_ADDR_SLICE_2 = 41,
    SYS_AT_INTR_FUNC_SVC_POLICING_STATUS_ADDR_SLICE_3 = 42,
    SYS_AT_INTR_FUNC_TS_CAPTURE_FIFO = 43,
    SYS_AT_INTR_FUNC_TOD_PULSE = 44,
    SYS_AT_INTR_FUNC_SYNC_PULSE0 = 45,
    SYS_AT_INTR_FUNC_SYNC_PULSE1 = 46,
    SYS_AT_INTR_FUNC_SYNC_CODE_IN_RDY0 = 47,
    SYS_AT_INTR_FUNC_SYNC_CODE_IN_RDY1 = 48,
    SYS_AT_INTR_FUNC_SYNC_CODE_IN_ACC_CHG0 = 49,
    SYS_AT_INTR_FUNC_SYNC_CODE_IN_ACC_CHG1 = 50,
    SYS_AT_INTR_FUNC_HATA_TX_TS_FIFO_0_START  = 51,
    SYS_AT_INTR_FUNC_HATA_TX_TS_FIFO_0_END= 70,
    SYS_AT_INTR_FUNC_HATA_TX_TS_FIFO_1_START  = 71,
    SYS_AT_INTR_FUNC_HATA_TX_TS_FIFO_1_END  = 90,

    SYS_AT_INTR_MAX = 112
};
typedef enum sys_at_interrupt_type_e sys_at_interrupt_type_t;


enum sys_at_interrupt_mac_type_e
{
    SYS_AT_INTR_MAC_HSCTL1 = 0,
    SYS_AT_INTR_MAC_HSCTL = 1,
    SYS_AT_INTR_MAC_LINK_DOWN_0 = 2,
    SYS_AT_INTR_MAC_LINK_DOWN_7 = 9,
    SYS_AT_INTR_MAC_LINK_UP_0 = 10,
    SYS_AT_INTR_MAC_LINK_UP_7 = 17,
    SYS_AT_INTR_MAC_HATA_TS_TO_CPU_FIFO = 18,
    SYS_AT_INTR_MAC_TO_RLM_VALID = 19,
    SYS_AT_INTR_MAC_MAX = 20
};
typedef enum sys_at_interrupt_mac_type_e sys_at_interrupt_mac_type_t;


#define DEF_D(RegName, bit) \
    }; \
  uint32 RegName##_sub_low_list_at_##bit[] = {

#define DEF_F(RegName, bit, InstNum, bitmap) \
    RegName##_t | InstNum << 24 | bitmap << 16,

#define DEF_F_NULL(bit) \
    0,

#define DEF_DD(RegName, bit) \
    }; \
    uint32 RegName##_sub_low_list_at_##bit[] = {

#define DEF_FF_NULL(RegName, bit) \
    0,

#define DEF_FF(RegName, bit, InstNum, bitmap) \
    RegName##_t | InstNum << 24 | bitmap << 16,

#define DEF_DD1(RegName, bit)
#define DEF_FF1(RegName, bit)
#define FATAL_BASE(sub_type, value)
#define NORMAL_BASE(sub_type, value)
#define FATAL_BASE_ARRAY_START
#define NORMAL_BASE_ARRAY_START
#define FATAL_BASE_ARRAY_END
#define NORMAL_BASE_ARRAY_END

uint32 sub_low_1st_at[] = {0,
#include "sys_at_interrupt.h"
};

#undef DEF_D
#undef DEF_F
#undef DEF_F_NULL
#undef DEF_DD
#undef DEF_FF_NULL
#undef DEF_FF
#undef DEF_DD1
#undef DEF_FF1
#undef FATAL_BASE
#undef NORMAL_BASE
#undef FATAL_BASE_ARRAY_START
#undef NORMAL_BASE_ARRAY_START
#undef FATAL_BASE_ARRAY_END
#undef NORMAL_BASE_ARRAY_END


/*Generate the sub low table list*/
#define DEF_D(RegName, bit)
#define DEF_F(RegName, bit, InstNum, bitmap)
#define DEF_F_NULL(bit)
#define FATAL_BASE(sub_type, value)
#define NORMAL_BASE(sub_type, value)
#define FATAL_BASE_ARRAY_START
#define NORMAL_BASE_ARRAY_START
#define FATAL_BASE_ARRAY_END
#define NORMAL_BASE_ARRAY_END

#define DEF_DD(RegName, bit) \
    }; \
  sys_intr_tbl_array_t RegName##_sub_list_at[] = {

#define DEF_FF_NULL(RegName, bit) \
    {NULL, 0},

#define DEF_FF(RegName, bit, InstNum, bitmap) \
    {RegName##_sub_low_list_at_##bit, sizeof(RegName##_sub_low_list_at_##bit)/sizeof(RegName##_sub_low_list_at_##bit[0])},

#define DEF_DD1(RegName, bit) \
    }; \
  sys_intr_tbl_array_t RegName##_sub_list_at[] = {

#define DEF_FF1(RegName, bit) \
    {RegName##_sub_low_list_at_##bit, sizeof(RegName##_sub_low_list_at_##bit)/sizeof(RegName##_sub_low_list_at_##bit[0])},

sys_intr_tbl_array_t sub_1st_at[] = {{0, 0},
#include "sys_at_interrupt.h"
};

#undef DEF_D
#undef DEF_F
#undef DEF_F_NULL
#undef DEF_DD
#undef DEF_FF_NULL
#undef DEF_FF
#undef DEF_DD1
#undef DEF_FF1
#undef FATAL_BASE
#undef NORMAL_BASE
#undef FATAL_BASE_ARRAY_START
#undef NORMAL_BASE_ARRAY_START
#undef FATAL_BASE_ARRAY_END
#undef NORMAL_BASE_ARRAY_END


#define DEF_D(RegName, bit)
#define DEF_F(RegName, bit, InstNum, bitmap)
#define DEF_F_NULL(bit)
#define DEF_DD(RegName, bit)
#define DEF_FF(RegName, bit, InstNum, bitmap)
#define DEF_FF_NULL(RegName, bit)
#define DEF_DD1(RegName, bit)
#define DEF_FF1(RegName, bit)

#define FATAL_BASE_ARRAY_START \
    uint16 fatal_sub_base_at[] = {

#define FATAL_BASE(sub_type, value) \
    value,

#define FATAL_BASE_ARRAY_END \
    };

#define NORMAL_BASE_ARRAY_START \
    uint16 normal_sub_base_at[] = {

#define NORMAL_BASE(sub_type, value) \
    value,

#define NORMAL_BASE_ARRAY_END \
    };

#include "sys_at_interrupt.h"

#define SUB_TABLE_LIST(RegName)  RegName##_sub_list_at


struct sys_intr_info_s{
    uint8 pp_id;
    uint8 dp_id;
};
typedef struct sys_intr_info_s sys_intr_info_t;

extern int32 sys_usw_qos_fcdl_state_isr(uint8 lchip, uint16 mac_id);
extern int32 _sys_usw_interrupt_dispatch_normal(uint8 lchip, uint32* status);
extern int32 _sys_usw_interrupt_dispatch_fatal(uint8 lchip, uint32* status);
extern int32 _sys_usw_intr_log_normal_intr(uint8 lchip, sys_intr_abnormal_log_t log_intr);

int32
sys_at_interrupt_dispatch_func_ctcmac(uint8 lchip, uint32 int_type, void* bmp)
{
    uint32 cmd = 0;
    uint32 value = 0;
    uint32 mask = 0;    
    uint32 sup_value = 0;
    sys_usw_intr_isr_data_t isr_data;
    uint8 oper_bmp = 0;
    uint8 ins = 0;

    sal_memset(&isr_data, 0, sizeof(sys_usw_intr_isr_data_t));
    oper_bmp = ((lchip - SYS_PP_BASE(lchip)) >= PP_NUM_PER_CORE) ? 0x80 : 0x40;/* all function interrupt tables are core-level */
    cmd = DRV_IOR(InterruptLogFuncMac_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, 0, ((uint64)oper_bmp << 32)|cmd, &sup_value));

    for (ins = 0; ins < 20; ins++)
    {
        if (!CTC_IS_BIT_SET(sup_value, ins))
        {
            continue;
        }

        cmd = DRV_IOR(CtcMacCtlInterruptFunc_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_VAL_SET + ins * INTR_INDEX_MAX, ((uint64)oper_bmp << 32)|cmd, &value));
        cmd = DRV_IOR(CtcMacCtlInterruptFunc_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_MASK_SET + ins * INTR_INDEX_MAX, ((uint64)oper_bmp << 32)|cmd, &mask));

        if (p_usw_intr_master[lchip]->mac_isr)
        {
            isr_data.status[0] = value & (~mask);
            isr_data.ins = ins;
            p_usw_intr_master[lchip]->mac_isr(lchip, int_type, &isr_data);
            }
        cmd = DRV_IOW(CtcMacCtlInterruptFunc_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_VAL_RESET + ins * INTR_INDEX_MAX, ((uint64)oper_bmp << 32)|cmd, isr_data.status));
    }

    return CTC_E_NONE;
}

STATIC INLINE uint8
_sys_at_interrupt_need_release(uint8 lchip, uint32 tbl_id_mux)
{
    uint32 mc_mac_valid[2];
    uint16 tbl_id;
    uint8 mc_mac_invalid = 0;
    uint8 core_id = 0;
    uint8 oper_bmp;
    uint8 ins_id;
    uint8 is_single_core = !SYS_VCHIP_DUAL_CORE_MODE(lchip);

    if (tbl_id_mux == 0)
    {
        return 0;
    }

    tbl_id = tbl_id_mux & 0xffff;
    oper_bmp = ((tbl_id_mux >> 16) & 0xFF);/* read core0 */
    ins_id = (tbl_id_mux >> 24) & 0xFF;

    /* 1. no need release interrupt table of unused mcmac,
     *     1.1 get core 0 and core 1 valid mcmac bmp */
    sys_usw_port_api_get_mac_group_valid(lchip, 0, &mc_mac_valid[0]);
    if (!is_single_core)
    {
        sys_usw_port_api_get_mac_group_valid(SYS_PP_BASE(lchip) + PP_NUM_PER_CORE, 1, &mc_mac_valid[1]);
    }
    /*     1.2 check unused mcmac */
    core_id = (oper_bmp >> 7) & 0x1;
    if (tbl_id == McMacInterruptNormal_t || tbl_id == McpuInterruptNormal_t || tbl_id == McPcs800InterruptNormal_t || 
        tbl_id == McHataInterruptNormal_t || tbl_id == CtcMacCtlInterruptNormal_t || tbl_id == McpuInterruptNormal_t)
    {
        mc_mac_invalid = !CTC_IS_BIT_SET(mc_mac_valid[core_id], ins_id);
    }
    if (CtcHsCtlInterruptNormal_t == tbl_id || CtcHsCtlInterruptNormal1_t == tbl_id)
    {
        mc_mac_invalid = !CTC_IS_BIT_SET(mc_mac_valid[core_id], (ins_id/2));
    }
    if (mc_mac_invalid)
    {
        return 0;
    }

    /* 2. no need release PEER_DP or PEER_PP table when single core */
    if (is_single_core && (ins_id >= (TABLE_ADDR_NUM(lchip, tbl_id) / 2)) &&
        (TABLE_ENTRY_TYPE(lchip, tbl_id) == MEM_TYPE_PEER_PP || TABLE_ENTRY_TYPE(lchip, tbl_id) == MEM_TYPE_PEER_DP))
    {
        return 0;
    }

    /* 3. no need release OAM relatives tables without OAM module active in chip */
    if (MCHIP_FEATURE_EN(lchip, CTC_FEATURE_OAM) == 0 && 
        (OamAutoGenInterruptNormal_t == tbl_id || OamFwdInterruptNormal_t == tbl_id || OamFwdInterruptFatal_t == tbl_id ||
        OamHashInterruptFatal_t == tbl_id || OamHashInterruptNormal_t == tbl_id || OamParserInterruptFatal_t == tbl_id ||
        OamProcInterruptFatal_t == tbl_id || OamProcInterruptNormal_t == tbl_id))
    {
        return 0;
    }

    /* 4. no need release ECPU dma mask */
    if ((DmaCtlInterruptNormal_t == tbl_id || DmaCtlInterruptFatal_t == tbl_id) && ((ins_id == 1) || (ins_id == 2)))
    {
        return 0;
    }

    /* 5. no need release Log table */
    if (tbl_id == InterruptLogMacNormal_t || tbl_id == InterruptLogRlmDpNormal_t || tbl_id == InterruptLogRlmDpFatal_t)
    {
        return 0;
    }

    return 1;
}

int32
sys_at_interrupt_release_fatal(uint8 lchip, sys_intr_type_t* p_type, uint32 enable)
{
    uint32 sub_tbl_id = 0;
    uint32 tbl_id_low = 0;
    uint32 end_table_id = 0;
    uint32 cmd = 0;
    int32 ret = CTC_E_NONE;
    uint32 mask[CTC_INTR_STAT_SIZE];
    uint16 intr_base = 0;
    uint8 oper_bmp = 0;
    uint8 ins_num = 0;

    CTC_BMP_INIT(mask);
    SYS_INTETRUPT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    /* relase mask of all fatal interrupt */
    INTR_SUB_TYPE_CHECK(p_type->sub_intr, p_usw_intr_master[lchip]->fatal_sub_cnt);

    /* now only support clear mask */
    if (!enable)
    {
        ret = CTC_E_NOT_SUPPORT;
        return ret;
    }

    sub_tbl_id = p_usw_intr_master[lchip]->p_intr_sub_abnormal[SYS_INTR_CHIP_FATAL].p_array[p_type->sub_intr];

    if (p_usw_intr_master[lchip]->p_intr_low_fatal[p_type->sub_intr].array_size)
    {
        tbl_id_low =  p_usw_intr_master[lchip]->p_intr_low_fatal[p_type->sub_intr].p_array[p_type->low_intr];
    }

    intr_base = p_usw_intr_master[lchip]->fatal_sub_base[p_type->sub_intr];
    if (p_usw_intr_master[lchip]->p_intr_fatal_end_tbl[p_type->low_intr + intr_base].array_size)
    {
        end_table_id = p_usw_intr_master[lchip]->p_intr_fatal_end_tbl[p_type->low_intr + intr_base].p_array[p_type->lvl4_intr];
    }

    //-SYS_INTR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP,"fatal sub-intr-table:%s\n", DRV_TABLE_NAME(lchip, sub_tbl_id&0xffff));
    //-SYS_INTR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP,"fatal low-intr-table:%s\n", DRV_TABLE_NAME(lchip, tbl_id_low&0xffff));
    //-SYS_INTR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP,"fatal end-intr-table:%s\n", DRV_TABLE_NAME(lchip, end_table_id&0xffff));

    if (_sys_at_interrupt_need_release(lchip, end_table_id))
    {
        oper_bmp = (end_table_id >> 16) & 0xFF;/* read core0 */
        ins_num = (end_table_id >> 24) & 0xFF;

        cmd = DRV_IOR(end_table_id & 0xFFFF, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_MASK_SET + ins_num * INTR_INDEX_MAX, ((uint64)oper_bmp << 32) | cmd, mask));

        oper_bmp = ((end_table_id >> 16) & 0xFF) | 0xC0;/* write core0 & core1 */
        cmd = DRV_IOW(end_table_id & 0xFFFF, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_MASK_RESET + ins_num * INTR_INDEX_MAX, ((uint64)oper_bmp << 32) | cmd, mask));
    }

    if (_sys_at_interrupt_need_release(lchip, tbl_id_low))
    {
        /* clear mask of low-level interrupt */
        oper_bmp = (tbl_id_low >> 16) & 0xFF;/* read core0 */
        ins_num = (tbl_id_low >> 24) & 0xFF;

        cmd = DRV_IOR(tbl_id_low & 0xFFFF, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_MASK_SET + ins_num * INTR_INDEX_MAX, ((uint64)oper_bmp << 32) | cmd, mask));

        oper_bmp = ((tbl_id_low >> 16) & 0xFF) | 0xC0;/* write core0 & core1 */
        cmd = DRV_IOW(tbl_id_low & 0xFFFF, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_MASK_RESET + ins_num * INTR_INDEX_MAX, ((uint64)oper_bmp << 32) | cmd, mask));
    }

    if (_sys_at_interrupt_need_release(lchip, sub_tbl_id))
    {
        /* clear mask of sub-level interrupt */
        oper_bmp = (sub_tbl_id >> 16) & 0xFF;/* read core0 */
        ins_num = (sub_tbl_id >> 24) & 0xFF;

        cmd = DRV_IOR(sub_tbl_id & 0xFFFF, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_MASK_SET + ins_num * INTR_INDEX_MAX, ((uint64)oper_bmp << 32) | cmd, mask));

        oper_bmp = ((sub_tbl_id >> 16) & 0xFF) | 0xC0;/* write core0 & core1 */
        cmd = DRV_IOW(sub_tbl_id & 0xFFFF, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_MASK_RESET + ins_num * INTR_INDEX_MAX, ((uint64)oper_bmp << 32) | cmd, mask));
    }

    /* no need to clear mask of sup-level interrupt, as MapIntrlogFatalLocal is read only */
    return CTC_E_NONE;
}

int32
sys_at_interrupt_release_normal(uint8 lchip, sys_intr_type_t* p_type, uint32 enable)
{
    uint32 sub_tbl_id = 0;
    uint32 tbl_id_low = 0;
    uint32 end_tbl_id = 0;
    uint32 cmd = 0;
    int32 ret = CTC_E_NONE;
    uint32 mask[CTC_INTR_STAT_SIZE] = {0};
    uint16 intr_base = 0;
    uint8 oper_bmp = 0;
    uint8 ins_num = 0;

    CTC_BMP_INIT(mask);
    SYS_INTETRUPT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    /* relase mask of all fatal interrupt */
    INTR_SUB_TYPE_CHECK(p_type->sub_intr, p_usw_intr_master[lchip]->normal_sub_cnt);

    /* now only support clear mask */
    if (!enable)
    {
        ret = CTC_E_NOT_SUPPORT;
        return ret;
    }

    sub_tbl_id = p_usw_intr_master[lchip]->p_intr_sub_abnormal[SYS_INTR_CHIP_NORMAL].p_array[p_type->sub_intr];

    if(p_usw_intr_master[lchip]->p_intr_low_normal[p_type->sub_intr].array_size)
    {
        tbl_id_low = p_usw_intr_master[lchip]->p_intr_low_normal[p_type->sub_intr].p_array[p_type->low_intr];
    }

    intr_base = p_usw_intr_master[lchip]->normal_sub_base[p_type->sub_intr];
    if(p_usw_intr_master[lchip]->p_intr_normal_end_tbl[p_type->low_intr + intr_base].array_size)
    {
        end_tbl_id = p_usw_intr_master[lchip]->p_intr_normal_end_tbl[p_type->low_intr + intr_base].p_array[p_type->lvl4_intr];
    }

    //-SYS_INTR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP,"normal sub-intr-table:%s\n", DRV_TABLE_NAME(lchip, sub_tbl_id&0xffff));
    //-SYS_INTR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP,"normal low-intr-table:%s\n", DRV_TABLE_NAME(lchip, tbl_id_low&0xffff));
    //-SYS_INTR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP,"normal end-intr-table:%s\n", DRV_TABLE_NAME(lchip, end_tbl_id&0xffff));

    if (_sys_at_interrupt_need_release(lchip, end_tbl_id))
    {
        /* clear mask of low-level interrupt */
        oper_bmp = ((end_tbl_id >> 16) & 0xFF);/* read core0 */
        ins_num = (end_tbl_id >> 24) & 0xFF;

        cmd = DRV_IOR(end_tbl_id & 0xFFFF, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_MASK_SET + ins_num * INTR_INDEX_MAX, ((uint64)oper_bmp << 32) | cmd, mask));
        if ((end_tbl_id & 0xFFFF) == McMacInterruptNormal_t)
        {
            mask[0] = 0;           /*intRxLintFaul/intRxLintFault/intRxLocalFault/intRxRemoteFault*/
            mask[1] = 0xFFFF0000;  /*intMcMacTxPauseTypeMismatch/intMcMacRxPauseTypeMismatch/intMcMacRxPauseLockDetect/
                                     intStatsRam0ParityError/mcMacTxBuffParityError/mcMacMiiRxTsBuff0ParityError/intTxBuffOverrun*/
            mask[2] = 0;           /*intRxBuff[0-3]Overrun*/
            mask[4] = 0x00FFFFFF;  /* intMiiTxBuffUnderrun, 8, {4,24,8} */
            mask[5] = 0xFFFFFFDF;  /*mcMacMiiTxBuffParityError, 1, {5,5,1} */
        }
        /* not release intrRxLocalDegraded/intrRxRemoteDegraded/intrRxFecDegraded */
        if (McPcs400InterruptNormal_t == (end_tbl_id & 0xFFFF))
        {
            mask[0] = 0xFFF80700;
        }

        /* not release intrTxBufOverrunLane0-7 */
        if (McPcs800InterruptNormal_t == (end_tbl_id & 0xFFFF))
        {
            mask[0] = 0xFFFFFC03;
        }

        /* not release intrRxAsyncFifoOverrunLane0Mcu/1/2/3Mcu intrTxAsyncFifoOverrunLane0/1/2/3Mcu */
        if (CtcHsCtlInterruptNormal_t == (end_tbl_id & 0xFFFF) || CtcHsCtlInterruptNormal1_t == (end_tbl_id & 0xFFFF))
        {
            mask[0] = 0xFFFC003F;
        }

        /* not release anRemoteAnegErr/anRemoteLinkFailure/anRemoteOffline/anComplete0*/
        if (SharedPcsInterruptNormal_t == (end_tbl_id & 0xFFFF))
        {
            mask[0] = 0xFFFF0000;
        }

        /* not release intRxLintFault/intRxRemoteFault/intRxLocalFault/intRxLinkFault*/
        if (SharedMiiInterruptNormal_t == (end_tbl_id & 0xFFFF))
        {
            mask[0] = 0xFFFF0000;
        }
        oper_bmp = ((end_tbl_id >> 16) & 0xFF) | 0xC0;/* write core0 & core1 */
        cmd = DRV_IOW(end_tbl_id & 0xFFFF, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_MASK_RESET + ins_num * INTR_INDEX_MAX, ((uint64)oper_bmp << 32) | cmd, mask));
    }

    if (_sys_at_interrupt_need_release(lchip, tbl_id_low))
    {
        /* clear mask of low-level interrupt */
        oper_bmp = ((tbl_id_low >> 16) & 0xFF);/* read core0 */
        ins_num = (tbl_id_low >> 24) & 0xFF;

        cmd = DRV_IOR(tbl_id_low & 0xFFFF, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_MASK_SET + ins_num * INTR_INDEX_MAX, ((uint64)oper_bmp << 32) | cmd, mask));

        oper_bmp = ((tbl_id_low >> 16) & 0xFF) | 0xC0;/* write core0 & core1 */
        cmd = DRV_IOW(tbl_id_low & 0xFFFF, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_MASK_RESET + ins_num * INTR_INDEX_MAX, ((uint64)oper_bmp << 32) | cmd, mask));
    }

    if(_sys_at_interrupt_need_release(lchip, sub_tbl_id))
    {
        /* clear mask of sub-level interrupt */
        oper_bmp = ((sub_tbl_id >> 16) & 0xFF);/* read core0 */
        ins_num = (sub_tbl_id >> 24) & 0xFF;

        cmd = DRV_IOR(sub_tbl_id & 0xFFFF, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_MASK_SET + ins_num * INTR_INDEX_MAX, ((uint64)oper_bmp << 32) | cmd, mask));

        /* not release intTxqmMux1TxInputConflict */
        if (MacAggCtlInterruptNormal_t == (sub_tbl_id & 0xFFFF))
        {
            mask[0] = 0xFFFFFFFB;
        }
        oper_bmp = ((sub_tbl_id >> 16) & 0xFF) | 0xC0;/* write core0 & core1 */
        cmd = DRV_IOW(sub_tbl_id & 0xFFFF, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_MASK_RESET + ins_num * INTR_INDEX_MAX, ((uint64)oper_bmp << 32) | cmd, mask));
    }

    /* no need to clear mask of sup-level interrupt, as MapIntrlogNormalLocal is read only */
    return CTC_E_NONE;
}

int32 sys_at_interrupt_db_init(uint8 lchip)
{
    uint8 intr_idx = 0;
    sys_intr_func_intr_info_t* p_func_intr_at = NULL;

    p_usw_intr_master[lchip]->p_intr_fatal_end_tbl = SUB_TABLE_LIST(LogFatalEndTable);
    p_usw_intr_master[lchip]->p_intr_normal_end_tbl = SUB_TABLE_LIST(LogNormalEndTable);
    p_usw_intr_master[lchip]->p_intr_low_fatal = SUB_TABLE_LIST(MapIntrLogFatalLocal);
    p_usw_intr_master[lchip]->p_intr_low_normal = SUB_TABLE_LIST(MapIntrLogNormalLocal);
    p_usw_intr_master[lchip]->p_intr_sub_abnormal = SUB_TABLE_LIST(SupIntrGenCtl);
    p_usw_intr_master[lchip]->fatal_sub_base = fatal_sub_base_at;
    p_usw_intr_master[lchip]->normal_sub_base = normal_sub_base_at;

    p_usw_intr_master[lchip]->fatal_sub_cnt = sizeof(SUB_TABLE_LIST(MapIntrLogFatalLocal)) / sizeof(sys_intr_tbl_array_t);
    p_usw_intr_master[lchip]->normal_sub_cnt =  sizeof(SUB_TABLE_LIST(MapIntrLogNormalLocal)) / sizeof(sys_intr_tbl_array_t);
    p_usw_intr_master[lchip]->pp_base[0] = 0;
    p_usw_intr_master[lchip]->pp_base[1] = PP_NUM_PER_CORE;
    p_usw_intr_master[lchip]->intr_base = SYS_AT_INTR_CPU_SUB_ECPU_00;
    p_usw_intr_master[lchip]->intr_max = (drv_vchip_get_core_num(lchip) == 2)?(SYS_AT_INTR_MAX+SYS_AT_INTR_FUNC_HATA_TX_TS_FIFO_1_END):SYS_AT_INTR_FUNC_HATA_TX_TS_FIFO_1_END; 
    p_usw_intr_master[lchip]->intr_word_num = 7;
    p_usw_intr_master[lchip]->intr[SYS_INTR_FUNC_MAC].isr = sys_at_interrupt_dispatch_func_ctcmac;
    p_usw_intr_master[lchip]->intr[SYS_INTR_FUNC_MAC].valid = 1;

    p_usw_intr_master[lchip]->p_intr_func = mem_malloc(MEM_SYSTEM_MODULE, sizeof(sys_intr_func_intr_info_t)*SYS_AT_INTR_MAX);
    if (!p_usw_intr_master[lchip]->p_intr_func)
    {
        return CTC_E_NO_MEMORY;
    }
    sal_memset(p_usw_intr_master[lchip]->p_intr_func, 0, sizeof(sys_intr_func_intr_info_t)*SYS_AT_INTR_MAX);

    for (intr_idx = 0; intr_idx < SYS_AT_INTR_MAX; intr_idx++)
    {
        p_func_intr_at = &p_usw_intr_master[lchip]->p_intr_func[intr_idx];
        p_func_intr_at->tbl_size = 3;
        switch (intr_idx)
        {
            case SYS_AT_INTR_FUNC_MAC_EVENT:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                //p_func_intr_at->sub_tbl_id = CtcMacCtlInterruptFunc_t; process in sys_at_interrupt_dispatch_func_ctcmac
                p_func_intr_at->bit_offset = 0;
                p_func_intr_at->common_type = SYS_INTR_FUNC_MAC;                
                p_func_intr_at->tbl_size = 1;

                break;
            case SYS_AT_INTR_FUNC_CPU_MAC:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->sub_tbl_id = CpuMacProcInterruptFunc_t;
                p_func_intr_at->bit_offset = 1;
                p_func_intr_at->common_type = SYS_INTR_FUNC_CPU_MAC;                
                p_func_intr_at->tbl_size = 5;
                break;

            case SYS_AT_INTR_FUNC_BSR_ERM_MON:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 2;
                p_func_intr_at->common_type = SYS_INTR_FUNC_BSR_ERM_MON;
                break;

            case SYS_AT_INTR_FUNC_BSR_IRM_MON:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 3;
                p_func_intr_at->common_type = SYS_INTR_FUNC_BSR_IRM_MON;
                break;

            case SYS_AT_INTR_FUNC_OAM_DEFECT_CACHE:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 4;
                p_func_intr_at->common_type = SYS_INTR_FUNC_OAM_DEFECT_CACHE;
                break;

            case SYS_AT_INTR_FUNC_OAM_AUTO_GEN:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->sub_tbl_id = OamAutoGenInterruptFunc_t;
                p_func_intr_at->bit_offset = 5;
                p_func_intr_at->common_type = SYS_INTR_FUNC_OAM_AUTO_GEN;
                break;

            case SYS_AT_INTR_FUNC_OAM_TWAMP:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 6;
                p_func_intr_at->common_type = SYS_INTR_FUNC_OAM_TWAMP;
                break;

            case SYS_AT_INTR_FUNC_FIB_ACC_LEARN_OUT_FIFO:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 7;
                p_func_intr_at->common_type = SYS_INTR_FUNC_FIB_ACC_LEARN_OUT_FIFO;
                break;

            case SYS_AT_INTR_FUNC_MISC_EVENT:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
#ifndef EMULATION_ENV
                //p_func_intr_at->sub_tbl_id = CtcMiscCtlInterruptFunc_t;
#endif
                p_func_intr_at->bit_offset = 8;
                p_func_intr_at->common_type = SYS_INTR_FUNC_MISC_EVENT;
                break;

            case SYS_AT_INTR_FUNC_MACSEC:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->sub_tbl_id = InterruptVecXSecFunc_t;
                p_func_intr_at->bit_offset = 13;
                p_func_intr_at->common_type = SYS_INTR_FUNC_MACSEC;
                p_func_intr_at->tbl_size = 1;
                break;

            case SYS_AT_INTR_FUNC_PCIE_BURST_DONE:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->sub_tbl_id = PcieIntfInterruptFunc_t;
                p_func_intr_at->bit_offset = 14;
                p_func_intr_at->common_type = SYS_INTR_PCIE_BURST_DONE;                
                p_func_intr_at->tbl_size = 1;
                break;

            case SYS_AT_INTR_FUNC_STATS_STATUS_ADDR_SLICE_0:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 15;
                p_func_intr_at->common_type = SYS_INTR_FUNC_STATS_STATUS_ADDR;
                break;

            case SYS_AT_INTR_FUNC_STATS_STATUS_ADDR_SLICE_1:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 16;
                p_func_intr_at->common_type = SYS_INTR_FUNC_STATS_STATUS_ADDR_SLICE_1;
                break;

            case SYS_AT_INTR_FUNC_STATS_STATUS_ADDR_SLICE_2:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 17;
                p_func_intr_at->common_type = SYS_INTR_FUNC_STATS_STATUS_ADDR_SLICE_2;
                break;

            case SYS_AT_INTR_FUNC_STATS_STATUS_ADDR_SLICE_3:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 18;
                p_func_intr_at->common_type = SYS_INTR_FUNC_STATS_STATUS_ADDR_SLICE_3;
                break;

            case SYS_AT_INTR_FUNC_IPFIX_USEAGE_OVERFLOW:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->sub_tbl_id = InterruptVecIpfixIpeOverflow_t;
                p_func_intr_at->bit_offset = 19;
                p_func_intr_at->common_type = SYS_INTR_FUNC_IPFIX_USEAGE_OVERFLOW;                
                p_func_intr_at->tbl_size = 1;
                break;

            case SYS_AT_INTR_FUNC_EPE_IPFIX_USEAGE_OVERFLOW:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->sub_tbl_id = InterruptVecIpfixEpeOverflow_t;
                p_func_intr_at->bit_offset = 20;
                p_func_intr_at->common_type = SYS_INTR_FUNC_EPE_IPFIX_USEAGE_OVERFLOW;                
                p_func_intr_at->tbl_size = 1;
                break;

            case SYS_AT_INTR_FUNC_STMCTL_STATE_SLICE_0:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 21;
                p_func_intr_at->common_type = SYS_INTR_FUNC_STMCTL_STATE;
                break;

            case SYS_AT_INTR_FUNC_STMCTL_STATE_SLICE_1:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 22;
                p_func_intr_at->common_type = SYS_INTR_FUNC_STMCTL_STATE_1;
                break;

            case SYS_AT_INTR_FUNC_STMCTL_STATE_SLICE_2:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 23;
                p_func_intr_at->common_type = SYS_INTR_FUNC_STMCTL_STATE_2;
                break;

            case SYS_AT_INTR_FUNC_STMCTL_STATE_SLICE_3:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 24;
                p_func_intr_at->common_type = SYS_INTR_FUNC_STMCTL_STATE_3;
                break;

            case SYS_AT_INTR_FUNC_SVC_POLICING_STATUS_ADDR_SLICE_0:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 25;
                p_func_intr_at->common_type = SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR;
                break;

            case SYS_AT_INTR_FUNC_SVC_POLICING_STATUS_ADDR_SLICE_1:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 26;
                p_func_intr_at->common_type = SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR_1;
                break;

            case SYS_AT_INTR_FUNC_SVC_POLICING_STATUS_ADDR_SLICE_2:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 27;
                p_func_intr_at->common_type = SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR_2;
                break;

            case SYS_AT_INTR_FUNC_SVC_POLICING_STATUS_ADDR_SLICE_3:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 28;
                p_func_intr_at->common_type = SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR_3;
                break;
            case SYS_AT_INTR_FUNC_TS_CAPTURE_FIFO:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 29;
                p_func_intr_at->common_type = SYS_INTR_FUNC_PTP_TS_CAPTURE_FIFO;
                break;
            case SYS_AT_INTR_FUNC_TOD_PULSE:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 30;
                p_func_intr_at->common_type = SYS_INTR_FUNC_PTP_TOD_PULSE_IN;
                break;
            case SYS_AT_INTR_FUNC_SYNC_PULSE0:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 31;
                p_func_intr_at->common_type = SYS_INTR_FUNC_PTP_SYNC_PULSE;
                break;
            case SYS_AT_INTR_FUNC_SYNC_PULSE1:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 32;
                p_func_intr_at->common_type = SYS_INTR_FUNC_PTP_SYNC_PULSE1;
                break;
            case SYS_AT_INTR_FUNC_SYNC_CODE_IN_RDY0:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 33;
                p_func_intr_at->common_type = SYS_INTR_FUNC_PTP_SYNC_CODE_IN_RDY;
                break;
            case SYS_AT_INTR_FUNC_SYNC_CODE_IN_RDY1:
                p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                p_func_intr_at->bit_offset = 34;
                p_func_intr_at->common_type = SYS_INTR_FUNC_PTP_SYNC_CODE_IN_RDY1;
                break;
            case SYS_AT_INTR_CPU_SUB_DECODE_0:
                //p_func_intr_at->tbl_id = HcpuIntr0Set_t;
                p_func_intr_at->bit_offset = 0;
                p_func_intr_at->common_type = SYS_INTR_CPU_SUB_DECODE_0;
                break;

            case SYS_AT_INTR_CPU_SUB_DECODE_1:
                //p_func_intr_at->tbl_id = HcpuIntr1Set_t;
                p_func_intr_at->bit_offset = 0;
                p_func_intr_at->common_type = SYS_INTR_CPU_SUB_DECODE_1;
                break;

            case SYS_AT_INTR_CPU_SUB_DECODE_2:
                //p_func_intr_at->tbl_id = HcpuIntr2Set_t;
                p_func_intr_at->bit_offset = 0;
                p_func_intr_at->common_type = SYS_INTR_CPU_SUB_DECODE_2;
                break;

            case SYS_AT_INTR_CPU_SUB_DECODE_3:
                //p_func_intr_at->tbl_id = HcpuIntr3Set_t;
                p_func_intr_at->bit_offset = 0;
                p_func_intr_at->common_type = SYS_INTR_CPU_SUB_DECODE_3;
                break;

            case SYS_AT_INTR_CPU_SUB_ECPU_00:
                p_func_intr_at->bit_offset = 0;
                p_func_intr_at->common_type = SYS_INTR_CPU_SUB_ECPU_00;
                break;

            case SYS_AT_INTR_CPU_SUB_ECPU_01:
                p_func_intr_at->bit_offset = 0;
                p_func_intr_at->common_type = SYS_INTR_CPU_SUB_ECPU_01;
                break;

            case SYS_AT_INTR_CPU_SUB_ECPU_10:
                p_func_intr_at->bit_offset = 0;
                p_func_intr_at->common_type = SYS_INTR_CPU_SUB_ECPU_10;
                break;

            case SYS_AT_INTR_CPU_SUB_ECPU_11:
                p_func_intr_at->bit_offset = 0;
                p_func_intr_at->common_type = SYS_INTR_CPU_SUB_ECPU_11;
                break;

            case SYS_AT_INTR_CPU_SUB_DMA:
                p_func_intr_at->tbl_id = DmaCtlIntrFunc0_t;
                p_func_intr_at->bit_offset = 0;
                p_func_intr_at->common_type = SYS_INTR_DMA;
                break;

            case SYS_AT_INTR_CPU_SUB_UART:
                p_func_intr_at->tbl_id = UartInterrupt_t;
                p_func_intr_at->bit_offset = 0;
                p_func_intr_at->common_type = SYS_INTR_CPU_SUB_UART;
                break;

            case SYS_AT_INTR_CPU_SUB_QSPI:
                //p_func_intr_at->tbl_id = QspiFuncInterrupt_t;
                p_func_intr_at->bit_offset = 0;
                p_func_intr_at->common_type = SYS_INTR_CPU_SUB_QSPI;
                break;

            case SYS_AT_INTR_CPU_SUB_GPIO:
                p_func_intr_at->tbl_id = GpioIntrStatus_t;
                p_func_intr_at->bit_offset = 0;
                p_func_intr_at->common_type = SYS_INTR_CPU_SUB_GPIO;
                break;

            default:
                if(SYS_AT_INTR_FUNC_HATA_TX_TS_FIFO_0_START <= intr_idx && intr_idx <= SYS_AT_INTR_FUNC_HATA_TX_TS_FIFO_1_END)
                {
                    p_func_intr_at->tbl_id = MapIntrVecFuncLocal_t;
                    p_func_intr_at->bit_offset = 37 + intr_idx - SYS_AT_INTR_FUNC_HATA_TX_TS_FIFO_0_START;
                    p_func_intr_at->common_type = SYS_INTR_FUNC_PTP_TX_TS_FIFO_0_START + intr_idx - SYS_AT_INTR_FUNC_HATA_TX_TS_FIFO_0_START;
                }

                break;
        }
    }

    return CTC_E_NONE;
}

/* This function is to get the corresponding position of specific intr type in intrvec table(SupCtlIntrVec) */
int32 sys_at_interrupt_get_intrvec_offset(uint8 lchip, uint32 intr_type, uint32 *p_offset)
{
    uint8 core_id = (intr_type >> 24) & 0xFF;

    CTC_PTR_VALID_CHECK(p_offset);

    switch (intr_type & 0xFFFFFF)
    {
        case SYS_INTR_CHIP_FATAL:
            *p_offset = SYS_AT_INTR_CHIP_FATAL;
            break;
        case SYS_INTR_CHIP_NORMAL:
            *p_offset = SYS_AT_INTR_CHIP_NORMAL;
            break;
        case SYS_INTR_FUNC_MAC:
            *p_offset = SYS_AT_INTR_FUNC_MAC_EVENT;
            break;
        case SYS_INTR_FUNC_CPU_MAC:
            *p_offset = SYS_AT_INTR_FUNC_CPU_MAC;
            break;
        case SYS_INTR_FUNC_BSR_ERM_MON:
            *p_offset = SYS_AT_INTR_FUNC_BSR_ERM_MON;
            break;
        case SYS_INTR_FUNC_BSR_IRM_MON:
            *p_offset = SYS_AT_INTR_FUNC_BSR_IRM_MON;
            break;
        case SYS_INTR_FUNC_OAM_DEFECT_CACHE:
            *p_offset = SYS_AT_INTR_FUNC_OAM_DEFECT_CACHE;
            break;
        case SYS_INTR_FUNC_OAM_AUTO_GEN:
            *p_offset = SYS_AT_INTR_FUNC_OAM_AUTO_GEN;
            break;
        case SYS_INTR_FUNC_OAM_TWAMP:
            *p_offset = SYS_AT_INTR_FUNC_OAM_TWAMP;
            break;
        case SYS_INTR_FUNC_FIB_ACC_LEARN_OUT_FIFO:
            *p_offset = SYS_AT_INTR_FUNC_FIB_ACC_LEARN_OUT_FIFO;
            break;
        case SYS_INTR_FUNC_MISC_EVENT:
            *p_offset = SYS_AT_INTR_FUNC_MISC_EVENT;
            break;
        case SYS_INTR_FUNC_MACSEC:
            *p_offset = SYS_AT_INTR_FUNC_MACSEC;
            break;
        case SYS_INTR_PCIE_BURST_DONE:
            *p_offset = SYS_AT_INTR_FUNC_PCIE_BURST_DONE;
            break;
        case SYS_INTR_FUNC_STATS_STATUS_ADDR:
            *p_offset = SYS_AT_INTR_FUNC_STATS_STATUS_ADDR_SLICE_0;
            break;
        case SYS_INTR_FUNC_STATS_STATUS_ADDR_SLICE_1:
            *p_offset = SYS_AT_INTR_FUNC_STATS_STATUS_ADDR_SLICE_1;
            break;
        case SYS_INTR_FUNC_STATS_STATUS_ADDR_SLICE_2:
            *p_offset = SYS_AT_INTR_FUNC_STATS_STATUS_ADDR_SLICE_2;
            break;
        case SYS_INTR_FUNC_STATS_STATUS_ADDR_SLICE_3:
            *p_offset = SYS_AT_INTR_FUNC_STATS_STATUS_ADDR_SLICE_3;
            break;
        case SYS_INTR_FUNC_IPFIX_USEAGE_OVERFLOW:
            *p_offset = SYS_AT_INTR_FUNC_IPFIX_USEAGE_OVERFLOW;
            break;
        case SYS_INTR_FUNC_EPE_IPFIX_USEAGE_OVERFLOW:
            *p_offset = SYS_AT_INTR_FUNC_EPE_IPFIX_USEAGE_OVERFLOW;
            break;
        case SYS_INTR_FUNC_STMCTL_STATE:
            *p_offset = SYS_AT_INTR_FUNC_STMCTL_STATE_SLICE_0;
            break;
        case SYS_INTR_FUNC_STMCTL_STATE_1:
            *p_offset = SYS_AT_INTR_FUNC_STMCTL_STATE_SLICE_1;
            break;
        case SYS_INTR_FUNC_STMCTL_STATE_2:
            *p_offset = SYS_AT_INTR_FUNC_STMCTL_STATE_SLICE_2;
            break;
        case SYS_INTR_FUNC_STMCTL_STATE_3:
            *p_offset = SYS_AT_INTR_FUNC_STMCTL_STATE_SLICE_3;
            break;
        case SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR:
            *p_offset = SYS_AT_INTR_FUNC_SVC_POLICING_STATUS_ADDR_SLICE_0;
            break;
        case SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR_1:
            *p_offset = SYS_AT_INTR_FUNC_SVC_POLICING_STATUS_ADDR_SLICE_1;
            break;
        case SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR_2:
            *p_offset = SYS_AT_INTR_FUNC_SVC_POLICING_STATUS_ADDR_SLICE_2;
            break;
        case SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR_3:
            *p_offset = SYS_AT_INTR_FUNC_SVC_POLICING_STATUS_ADDR_SLICE_3;
            break;
        case SYS_INTR_CPU_SUB_DECODE_0:
            *p_offset = SYS_AT_INTR_CPU_SUB_DECODE_0;
            break;
        case SYS_INTR_CPU_SUB_DECODE_1:
            *p_offset = SYS_AT_INTR_CPU_SUB_DECODE_1;
            break;
        case SYS_INTR_CPU_SUB_DECODE_2:
            *p_offset = SYS_AT_INTR_CPU_SUB_DECODE_2;
            break;
        case SYS_INTR_CPU_SUB_DECODE_3:
            *p_offset = SYS_AT_INTR_CPU_SUB_DECODE_3;
            break;
        case SYS_INTR_CPU_SUB_ECPU_00:
            *p_offset = SYS_AT_INTR_CPU_SUB_ECPU_00;
            break;
        case SYS_INTR_CPU_SUB_ECPU_01:
            *p_offset = SYS_AT_INTR_CPU_SUB_ECPU_01;
            break;
        case SYS_INTR_CPU_SUB_ECPU_10:
            *p_offset = SYS_AT_INTR_CPU_SUB_ECPU_10;
            break;
        case SYS_INTR_CPU_SUB_ECPU_11:
            *p_offset = SYS_AT_INTR_CPU_SUB_ECPU_11;
            break;
        case SYS_INTR_DMA:
            *p_offset = SYS_AT_INTR_CPU_SUB_DMA;
            break;
        case SYS_INTR_CPU_SUB_UART:
            *p_offset = SYS_AT_INTR_CPU_SUB_UART;
            break;
        case SYS_INTR_CPU_SUB_QSPI:
            *p_offset = SYS_AT_INTR_CPU_SUB_QSPI;
            break;
        case SYS_INTR_CPU_SUB_GPIO:
            *p_offset = SYS_AT_INTR_CPU_SUB_GPIO;
            break;
        case SYS_INTR_FUNC_PTP_SYNC_CODE_IN_ACC:
            *p_offset = SYS_AT_INTR_FUNC_SYNC_CODE_IN_ACC_CHG0;
            break;
        case SYS_INTR_FUNC_PTP_SYNC_CODE_IN_RDY:
            *p_offset = SYS_AT_INTR_FUNC_SYNC_CODE_IN_RDY0;
            break;
        case SYS_INTR_FUNC_PTP_SYNC_CODE_IN_RDY1:
            *p_offset = SYS_AT_INTR_FUNC_SYNC_CODE_IN_RDY1;
            break;
        case SYS_INTR_FUNC_PTP_TOD_PULSE_IN:
            *p_offset = SYS_AT_INTR_FUNC_TOD_PULSE;
            break;
        case SYS_INTR_FUNC_PTP_TS_CAPTURE_FIFO:
             *p_offset = SYS_AT_INTR_FUNC_TS_CAPTURE_FIFO;
             break;
        default:
            if(SYS_INTR_FUNC_PTP_TX_TS_FIFO_0_START <= (intr_type & 0xFFFFFF) && (intr_type & 0xFFFFFF) <= SYS_INTR_FUNC_PTP_TX_TS_FIFO_1_END)
            {
                *p_offset = SYS_AT_INTR_FUNC_HATA_TX_TS_FIFO_0_START + ((intr_type & 0xFFFFFF) - SYS_INTR_FUNC_PTP_TX_TS_FIFO_0_START);
            }
            else
            {
                *p_offset = 0xFFFFFFFF; /* invalid value */
                return CTC_E_NOT_SUPPORT;
            }
            break;
    }

    *p_offset = core_id * SYS_AT_INTR_MAX + *p_offset;

    return CTC_E_NONE;
}

int32 sys_at_interrupt_get_sup_info(uint8 lchip, uint32 intr_type, uint32 *p_sup_table_id, uint16 *p_bit_offset, uint32 *p_func_table_id)
{
    CTC_PTR_VALID_CHECK(p_sup_table_id);
    CTC_PTR_VALID_CHECK(p_bit_offset);

    switch (intr_type)
    {
        case SYS_INTR_CHIP_FATAL:
            *p_sup_table_id = MapIntrLogFatalLocal_t;
            *p_bit_offset = 0; /* no use */
            break;
        case SYS_INTR_CHIP_NORMAL:
            *p_sup_table_id = MapIntrLogNormalLocal_t;
            *p_bit_offset = 0; /* no use */
            break;

        case SYS_INTR_FUNC_MAC:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 0;
            break;

        case SYS_INTR_FUNC_CPU_MAC:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 1;
            break;

        case SYS_INTR_FUNC_BSR_ERM_MON:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 2;
            break;
        case SYS_INTR_FUNC_BSR_IRM_MON:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 3;
            break;
        case SYS_INTR_FUNC_BSR_CONGESTION:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 4;
            break;

        case SYS_INTR_FUNC_OAM_DEFECT_CACHE:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 5;
            break;
        case SYS_INTR_FUNC_OAM_AUTO_GEN:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 6;
            break;
        case SYS_INTR_FUNC_OAM_TWAMP:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 7;
            break;
        case SYS_INTR_FUNC_FIB_ACC_LEARN_OUT_FIFO:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 8;
            break;
        case SYS_INTR_FUNC_MISC_EVENT:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 9;
            break;
        case SYS_INTR_FUNC_MACSEC:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 13;
            break;
        case SYS_INTR_PCIE_BURST_DONE:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 14;
            break;
        case SYS_INTR_FUNC_STATS_STATUS_ADDR:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 15;
            break;
        case SYS_INTR_FUNC_STATS_STATUS_ADDR_SLICE_1:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 16;
            break;
        case SYS_INTR_FUNC_STATS_STATUS_ADDR_SLICE_2:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 17;
            break;
        case SYS_INTR_FUNC_STATS_STATUS_ADDR_SLICE_3:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 18;
            break;
        case SYS_INTR_FUNC_IPFIX_USEAGE_OVERFLOW:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 19;
            break;
        case SYS_INTR_FUNC_EPE_IPFIX_USEAGE_OVERFLOW:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 20;
            break;
        case SYS_INTR_FUNC_STMCTL_STATE:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 21;
            break;
        case SYS_INTR_FUNC_STMCTL_STATE_1:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 22;
            break;
        case SYS_INTR_FUNC_STMCTL_STATE_2:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 23;
            break;
        case SYS_INTR_FUNC_STMCTL_STATE_3:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 24;
            break;
        case SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 25;
            break;
        case SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR_1:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 26;
            break;
        case SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR_2:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 27;
            break;
        case SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR_3:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 28;
            break;
        case SYS_INTR_FUNC_PTP_TS_CAPTURE_FIFO:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 29;
            break;
        case SYS_INTR_FUNC_PTP_TOD_PULSE_IN:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 30;
            break;
        case SYS_INTR_FUNC_PTP_SYNC_PULSE:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 31;
            break;
        case SYS_INTR_FUNC_PTP_SYNC_PULSE1:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 32;
            break;
        case SYS_INTR_FUNC_PTP_SYNC_CODE_IN_RDY:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 33;
            break;
        case SYS_INTR_FUNC_PTP_SYNC_CODE_IN_RDY1:
            *p_sup_table_id = MapIntrVecFuncLocal_t;
            *p_bit_offset = 34;
            break;
        case SYS_INTR_CPU_SUB_DECODE_0:
            //*p_sup_table_id = HcpuIntr0Set_t;
            *p_bit_offset = 0;/* no use */
            break;
        case SYS_INTR_CPU_SUB_DECODE_1:
            //*p_sup_table_id = HcpuIntr1Set_t;
            *p_bit_offset = 0;/* no use */
            break;
        case SYS_INTR_CPU_SUB_DECODE_2:
            //*p_sup_table_id = HcpuIntr2Set_t;
            *p_bit_offset = 0;/* no use */
            break;
        case SYS_INTR_CPU_SUB_DECODE_3:
            //*p_sup_table_id = HcpuIntr3Set_t;
            *p_bit_offset = 0;/* no use */
            break;
        case SYS_INTR_CPU_SUB_ECPU_00:
            *p_sup_table_id = IntrIntCtl_t;
            *p_bit_offset = 0;/* no use */
            break;
        case SYS_INTR_CPU_SUB_ECPU_01:
            *p_sup_table_id = IntrIntCtl_t;
            *p_bit_offset = 0;/* no use */
            break;
        case SYS_INTR_CPU_SUB_ECPU_10:
            *p_sup_table_id = IntrIntCtl_t;
            *p_bit_offset = 0;/* no use */
            break;
        case SYS_INTR_CPU_SUB_ECPU_11:
            *p_sup_table_id = IntrIntCtl_t;
            *p_bit_offset = 0;/* no use */
            break;
        case SYS_INTR_DMA:
            *p_sup_table_id = DmaCtlIntrFunc0_t;
            *p_bit_offset = 0;/* no use */
            break;
        case SYS_INTR_CPU_SUB_UART:
            *p_sup_table_id = UartInterrupt_t;
            *p_bit_offset = 0;/* no use */
            break;
        case SYS_INTR_CPU_SUB_QSPI:
            //*p_sup_table_id = QspiFuncInterrupt_t;
            *p_bit_offset = 0;/* no use */
            break;
        case SYS_INTR_CPU_SUB_GPIO:
            *p_sup_table_id = GpioIntrStatus_t;
            *p_bit_offset = 0;/* no use */
            break;
        default:
            if(intr_type >= SYS_INTR_FUNC_PTP_TX_TS_FIFO_0_START && intr_type <= SYS_INTR_FUNC_PTP_TX_TS_FIFO_1_END)
            {
                *p_sup_table_id = MapIntrVecFuncLocal_t;
                *p_bit_offset = 37 + intr_type - SYS_INTR_FUNC_PTP_TX_TS_FIFO_0_START;
            }
            else
            {
                *p_sup_table_id = 0; /* invalid value, must keep value is 0 */
                *p_bit_offset = 0xFFFF; /* invalid value */
            }
            return CTC_E_NOT_SUPPORT;
            break;
    }

    if (p_func_table_id)
    {
        switch (intr_type)
        {
            case SYS_INTR_FUNC_MAC:
                *p_func_table_id = InterruptLogFuncMac_t;
                break;
            case SYS_INTR_FUNC_CPU_MAC:
                *p_func_table_id = CpuMacProcInterruptFunc_t;
                break;
            case SYS_INTR_FUNC_BSR_CONGESTION:
                *p_func_table_id = InterruptVecBufStoreCongestion_t;
                break;
            case SYS_INTR_FUNC_OAM_AUTO_GEN:
                *p_func_table_id = OamAutoGenPktInterruptFunc_t;
                break;
            case SYS_INTR_PCIE_BURST_DONE:
                *p_func_table_id = PcieIntfInterruptFunc_t;
                break;
            case SYS_INTR_FUNC_IPFIX_USEAGE_OVERFLOW:
                *p_func_table_id = InterruptVecIpfixIpeOverflow_t;
                break;
            case SYS_INTR_FUNC_EPE_IPFIX_USEAGE_OVERFLOW:
                *p_func_table_id = InterruptVecIpfixEpeOverflow_t;
                break;
            case SYS_INTR_FUNC_MACSEC:
                *p_func_table_id = InterruptVecXSecFunc_t;
                break;
            default:
                *p_func_table_id = 0;/* other type return invalid table id, include fatal and normal */
                break;
        }
    }

    return CTC_E_NONE;
}
/*Notice: In this function, sys_intr_type_t is at sys_at_interrupt_type_t */
int32
sys_at_interrupt_get_status_func(uint8 lchip, sys_intr_type_t* p_type, uint32* p_bmp)
{
    uint32 cmd = 0;
    uint32 value[CTC_INTR_STAT_SIZE] = {0};
    uint32 mask[CTC_INTR_STAT_SIZE] = {0};
    uint32 tbl_id = 0;
    uint8 ins_num = 0;
    uint8 oper_bmp = 0;
    uint8 index = 0;
    uint8 tbl_size = 0;

    oper_bmp = p_type->core_id ? 0x80 : 0x40;/* all function interrupt tables are core-level */

    if (p_usw_intr_master[lchip]->p_intr_func[p_type->intr].sub_tbl_id)
    {
        tbl_id = p_usw_intr_master[lchip]->p_intr_func[p_type->intr].sub_tbl_id;
        tbl_size = p_usw_intr_master[lchip]->p_intr_func[p_type->intr].tbl_size;
    }
    else
    {
        tbl_id = p_usw_intr_master[lchip]->p_intr_func[p_type->intr].tbl_id;        
        tbl_size = p_usw_intr_master[lchip]->intr_word_num;
    }

    ins_num = (tbl_id >> 24)&0xFF;
    tbl_id = tbl_id&0xFFFFFF;

    cmd = DRV_IOR((tbl_id), DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_VAL_SET + ins_num * INTR_INDEX_MAX, ((uint64)oper_bmp << 32)|cmd, value));
    cmd = DRV_IOR((tbl_id), DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_MASK_SET + ins_num * INTR_INDEX_MAX, ((uint64)oper_bmp << 32)|cmd, mask));


    for(index = 0; index < tbl_size; index++)
    {
        p_bmp[index] = value[index] & (~mask[index]);
    }

    return CTC_E_NONE;
}

#define ENCODE_TABLE_ID(tbl_id, ins_num, oper_bmp) \
    tbl_id | ins_num << 24 | oper_bmp << 16

/*Notice: In this function, sys_intr_type_t is at sys_at_interrupt_type_t */
int32
sys_at_interrupt_clear_status_func(uint8 lchip, sys_intr_type_t* p_type, uint32* bmp)
{
    uint32 cmd = 0;
    uint32 tbl_id = 0;
    uint32 sub_tbl_id = 0;
    uint32 sup_bmp[3] = {0};
    uint8 ins_num = 0;
    uint8 oper_bmp = 0;

    oper_bmp = p_type->core_id ? 0x80 : 0x40;

    if (p_usw_intr_master[lchip]->p_intr_func[p_type->intr].sub_tbl_id)
    {
        sub_tbl_id = p_usw_intr_master[lchip]->p_intr_func[p_type->intr].sub_tbl_id;
        tbl_id = p_usw_intr_master[lchip]->p_intr_func[p_type->intr].tbl_id;
    }
    else
    {
        tbl_id = p_usw_intr_master[lchip]->p_intr_func[p_type->intr].tbl_id;
    }

    /* for CtcMac interrupt, interrupt status is cleared in sys_at_interrupt_dispatch_func_ctcmac, 
     * just clear MapIntrVecFuncLocal.ctcMacEvent status here */
    if (sub_tbl_id)
    {
        /* Must be Function MapIntrVecFuncLocal */
        ins_num = (sub_tbl_id >> 24)&0xFF;
        sub_tbl_id = sub_tbl_id&0xFFFFFF;
        cmd = DRV_IOW((sub_tbl_id), DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_VAL_RESET + ins_num * INTR_INDEX_MAX, ((uint64)oper_bmp << 32)|cmd, bmp));

#if ((SDK_WORK_PLATFORM == 1) || ((0 == SDK_WORK_PLATFORM) && (1 == SDK_WORK_ENV)))  /* simulation */
        _sys_usw_interrupt_model_sim_value(lchip, ENCODE_TABLE_ID(sub_tbl_id, ins_num, oper_bmp), p_usw_intr_master[lchip]->p_intr_func[p_type->intr].common_type, bmp, FALSE);
#endif

        CTC_BMP_SET(sup_bmp, p_usw_intr_master[lchip]->p_intr_func[p_type->intr].bit_offset);
        ins_num = (tbl_id >> 24)&0xFF;
        tbl_id = tbl_id&0xFFFFFF;
        cmd = DRV_IOW((tbl_id), DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_VAL_RESET + ins_num * INTR_INDEX_MAX, ((uint64)oper_bmp << 32)|cmd, sup_bmp));

#if ((SDK_WORK_PLATFORM == 1) || ((0 == SDK_WORK_PLATFORM) && (1 == SDK_WORK_ENV)))  /* simulation */
        _sys_usw_interrupt_model_sim_value(lchip, ENCODE_TABLE_ID(tbl_id, ins_num, oper_bmp), p_usw_intr_master[lchip]->p_intr_func[p_type->intr].common_type, sup_bmp, FALSE);
#endif

    }
    else
    {
        /* Partial Function & Cpu Sub System */
        ins_num = (tbl_id >> 24)&0xFF;
        tbl_id = tbl_id&0xFFFFFF;
        cmd = DRV_IOW((tbl_id), DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, INTR_INDEX_VAL_RESET + ins_num * INTR_INDEX_MAX, ((uint64)oper_bmp << 32)|cmd, bmp));

#if ((SDK_WORK_PLATFORM == 1) || ((0 == SDK_WORK_PLATFORM) && (1 == SDK_WORK_ENV)))  /* simulation */
        _sys_usw_interrupt_model_sim_value(lchip, ENCODE_TABLE_ID(tbl_id, ins_num, oper_bmp), p_usw_intr_master[lchip]->p_intr_func[p_type->intr].common_type, bmp, FALSE);
#endif

    }

    return CTC_E_NONE;
}

int32
sys_at_interrupt_dispatch_func(uint8 lchip, uint32* p_status)/* p_status value from SupCtlIntrLog */
{

    sys_intr_type_t type;
    sys_intr_t* p_intr = NULL;
    uint32 status[CTC_INTR_STAT_SIZE] = {0};
    sys_intr_func_intr_info_t* p_func_intr_at;
    sys_intr_info_t intr_info;
    uint8 intr_base = 0;    
    uint8 intr_max = 0;
    uint8 intr_idx = 0;
    uint8 core_id = 0;

    sal_memset(&intr_info, 0, sizeof(sys_intr_info_t));
    /* mask core 1 Fatal/Normal/CPU_SUB_DECODE_{0...3} interrupt */
    p_status[3] &= 0xFFC0FFFF;

    intr_base = p_usw_intr_master[lchip]->intr_base;
    intr_max = p_usw_intr_master[lchip]->intr_max;

    for (intr_idx = intr_base; intr_idx < intr_max; intr_idx++)
    {
        if (!CTC_BMP_ISSET(p_status, intr_idx))
        {
            continue;
        }
        core_id = (intr_idx >= SYS_AT_INTR_MAX) ? 1: 0;
        p_func_intr_at = &p_usw_intr_master[lchip]->p_intr_func[intr_idx%SYS_AT_INTR_MAX];

        /*get intr status*/
        type.intr = intr_idx%SYS_AT_INTR_MAX;
        type.sub_intr = INVG;
        type.low_intr = INVG;
        type.slice_id = 0;
        type.core_id = core_id;
        sys_at_interrupt_get_status_func(lchip, &type, status);

        intr_info.pp_id =  p_usw_intr_master[lchip]->pp_base[type.core_id];

        if (SYS_AT_INTR_FUNC_IPFIX_USEAGE_OVERFLOW == type.intr || SYS_AT_INTR_FUNC_EPE_IPFIX_USEAGE_OVERFLOW == type.intr)
        {
            uint8 index = 0;
            do 
            {
                if (CTC_BMP_ISSET(p_status, index))
                {
                    intr_info.pp_id += index;
                    break;
                }
            index++;
            }while (index < 4);
        }

        p_intr = &(p_usw_intr_master[lchip]->intr[p_func_intr_at->common_type]);
        if (p_intr->is_event)
        {
            CTC_ERROR_RETURN(sys_at_interrupt_clear_status_func(lchip, &type, status));/* status keep original value */
        }

        if (p_intr->valid)
        {
            p_intr->occur_count++;
            if (p_intr->isr)
            {
                SYS_INTR_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Dispatch interrupt intr: %d, count: %d\n", p_func_intr_at->common_type, p_intr->occur_count);
                p_intr->isr(intr_info.pp_id + SYS_PP_BASE(lchip), p_func_intr_at->common_type, status);
            }
        }

        if (!p_intr->is_event)
        {
            CTC_ERROR_RETURN(sys_at_interrupt_clear_status_func(lchip, &type, status));
        }
    }

    return CTC_E_NONE;
}

static INLINE int32
sys_at_interrupt_normal_process(uint8 lchip, sys_intr_type_t* p_type, uint32 intr_bit, ctc_interrupt_abnormal_status_t* p_abnormal_status)
{    
    tbls_id_t intr_tbl = MaxTblId_t;
    int32 ret = 0;
    uint8 action_type = 0;
    uint8 ecc_or_parity = 0;  
    uint8 gchip = 0 ;
    
    sys_usw_interrupt_get_info(lchip, p_type, intr_bit, &intr_tbl, &action_type, &ecc_or_parity);
    
    if (ecc_or_parity)
    {
        /* function interrupt for process ecc or parity */
        sys_usw_interrupt_proc_ecc_or_parity(lchip, intr_tbl, intr_bit, p_abnormal_status->type);
    }
    else if (p_usw_intr_master[lchip]->event_cb[CTC_EVENT_ABNORMAL_INTR])
    {
        SYS_USW_INTR_ABNORMAL_LOG_PROCESS(lchip, CTC_INTR_CHIP_NORMAL, p_abnormal_status->type.sub_intr, 
        p_abnormal_status->type.low_intr, p_abnormal_status->status.bmp);
        ret = sys_usw_get_gchip_id(lchip, &gchip);
        if (0 == ret)
        {
            p_usw_intr_master[lchip]->event_cb[CTC_EVENT_ABNORMAL_INTR](gchip, p_abnormal_status);
        }
    }   
    
    return CTC_E_NONE;
}

int32
sys_at_intrrupt_isr_sup_normal(uint8 lchip, uint32 intr, void* p_data)
{
    uint32* p_sup_normal = (uint32*)p_data;
    sys_intr_type_t type;
    uint32 idx = 0;
    uint32 offset = 0;
    uint32 i = 0;
    uint32 j = 0;
    uint32 p = 0;
    ctc_interrupt_abnormal_status_t abnormal_status;
    ctc_intr_status_t* p_status = &(abnormal_status.status);
    int32 ret = CTC_E_NONE;
    uint32  sub_bmp[CTC_INTR_STAT_SIZE] = {0};
    uint32  low_bmp[CTC_INTR_STAT_SIZE] = {0};
    uint32  end_bmp[CTC_INTR_STAT_SIZE] = {0};
    uint16 mac_id = 0;   
    uint16 k = 0;
    uint8 loop = 0;
    uint8 low_level_valid = 0;
    uint8 end_level_valid = 0;
    
    sal_memset(&abnormal_status, 0, sizeof(abnormal_status));
    sal_memset(&type, 0, sizeof(sys_intr_type_t));

    type.intr = SYS_INTR_CHIP_NORMAL;
	type.core_id = ((lchip - SYS_PP_BASE(lchip)) >= PP_NUM_PER_CORE) ? 1 : 0;
    /* 2. get & clear sub interrupt status */
    for (i = 0; i < p_usw_intr_master[lchip]->normal_sub_cnt; i++)
    {
        low_level_valid = 0;
        end_level_valid = 0;
        idx = i / CTC_UINT32_BITS;
        offset = i % CTC_UINT32_BITS;

        if (0 == p_sup_normal[idx])
        {
            /* bypass 32Bit 0 */
            i = (idx + 1) * CTC_UINT32_BITS-1;
            continue;
        }

        if (!CTC_IS_BIT_SET(p_sup_normal[idx], offset))
        {
            continue;
        }
        type.sub_intr = i;
        type.low_intr = INVG;
        type.lvl4_intr = INVG;
        abnormal_status.type.lvl4_intr = 0;

        /* get sub interrupt status */
        _sys_usw_interrupt_get_status_normal(lchip, &type, sub_bmp);

        if (!sub_bmp[0] && !sub_bmp[1] && !sub_bmp[2] && !sub_bmp[3] && !sub_bmp[4] && !sub_bmp[5])
        {
            continue;
        }

        for (j = 0; j < CTC_INTR_STAT_SIZE * CTC_UINT32_BITS; j++)
        {
            if(!CTC_BMP_ISSET(sub_bmp, j))
            {
                continue;
            }
            sal_memset(low_bmp, 0, sizeof(low_bmp));
            abnormal_status.type.intr = CTC_INTR_CHIP_NORMAL;
            abnormal_status.type.sub_intr = i;
            abnormal_status.type.low_intr = j;

            /* get low interrupt status */
            type.low_intr = j;
            ret = _sys_usw_interrupt_get_status_normal(lchip, &type, low_bmp);
            if (ret < 0)
            {
                continue;
            }
            SYS_INTR_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "sup-intr:%d sub-intr:%d low-intr:%d\n",type.intr,type.sub_intr,type.low_intr);

            for(loop = 0; loop < CTC_INTR_STAT_SIZE; loop++)
            {
                if(low_bmp[loop])
                {
                    low_level_valid = 1;
                    break;
                }
            }

            if (!low_level_valid)
            {
                abnormal_status.type.intr = CTC_INTR_CHIP_NORMAL;
                abnormal_status.type.sub_intr = i;
                abnormal_status.type.low_intr = j;
                abnormal_status.action = CTC_INTERRUPT_FATAL_INTR_LOG;
                sys_at_interrupt_normal_process(lchip, &type, j, &abnormal_status);
                continue;
            }
            
                       
            /* process all low interrupt*/
            for (k = 0; k < CTC_INTR_STAT_SIZE * CTC_UINT32_BITS; k++)
            {
                if (!CTC_BMP_ISSET(low_bmp, k))
                {
                    continue;
                }

                sal_memset(end_bmp, 0, sizeof(end_bmp));
                type.lvl4_intr = k;
                abnormal_status.type.lvl4_intr = k;

                ret = _sys_usw_interrupt_get_status_normal(lchip, &type, end_bmp);
                if (ret < 0)
                {
                    continue;
                }

                end_level_valid = (end_bmp[0] || end_bmp[1] || end_bmp[2] || end_bmp[3] || end_bmp[4] || end_bmp[5]) ?1:0;
                if (!end_level_valid)
                {
                    abnormal_status.type.intr = CTC_INTR_CHIP_NORMAL;
                    abnormal_status.type.sub_intr = i;
                    sal_memcpy(p_status->bmp, low_bmp, sizeof(uint32)*CTC_INTR_STAT_SIZE);
                    abnormal_status.type.low_intr = j;
                    abnormal_status.action = CTC_INTERRUPT_FATAL_INTR_LOG;
                    sys_at_interrupt_normal_process(lchip, &type, k, &abnormal_status);
                    continue;
                }    
                
                /* exist end table id */
                for (p = 0; p < CTC_INTR_STAT_SIZE * CTC_UINT32_BITS; p++)
                {
                    if (!CTC_BMP_ISSET(end_bmp, p))
                    {
                        continue;
                    }
                    
                    if (k == 8 && j <= 19 && i == 0 && p >= 48 && p <= 55)
                    {
                        mac_id = j * 8 + p - 48;
                        mac_id += (type.core_id ? MCHIP_CAP(SYS_CAP_MAC_NUM_PER_DP) : 0);
                        sys_usw_qos_fcdl_state_isr(lchip, mac_id);
                        continue;
                    }

                    /* MapIntrLogNormalLocal bit4 is CtcMiscCtlInterruptNormal              -> i = 4 
                       CtcMiscCtlInterruptNormal bit3 is CpuMacProcInterruptNormal          -> j = 3
                       CpuMacProcInterruptNormal bit7 is QuadSgmacInterruptNormal           -> k = 7
                       QuadSgmacInterruptNormal bit18~bit19 is intSgmac0-1RxPauseLockDetect -> p = 18~19
                     */
                    if (k == 7 && j == 3 && i == 4 && p >= 18 && p <= 19)
                    {
                        mac_id = MCHIP_CAP(SYS_CAP_CPUMAC_ID_MIN) + p - 18;
                        mac_id += (type.core_id ? MCHIP_CAP(SYS_CAP_CPUMAC_NUM_PER_CORE) : 0);
                        sys_usw_qos_fcdl_state_isr(lchip, mac_id);
                        continue;
                    }
                
                    abnormal_status.type.intr = CTC_INTR_CHIP_NORMAL;
                    abnormal_status.type.sub_intr = i;
                    sal_memcpy(p_status->bmp, end_bmp, sizeof(uint32)*CTC_INTR_STAT_SIZE);
                    abnormal_status.type.low_intr = j;
                    abnormal_status.type.lvl4_intr = k;
                    abnormal_status.action = CTC_INTERRUPT_FATAL_INTR_LOG;
                    sys_at_interrupt_normal_process(lchip, &type, p, &abnormal_status);
                }

                if (end_level_valid)
                {
                    /* clear end interrupt status in one time */
                    CTC_ERROR_RETURN(_sys_usw_interrupt_clear_status_normal(lchip, &type, end_bmp));  
                }
            }      

            if (low_level_valid)
            {
                type.lvl4_intr = INVG;
                /* clear low interrupt status in one time */
                CTC_ERROR_RETURN(_sys_usw_interrupt_clear_status_normal(lchip, &type, low_bmp));
            }
        }
        
        /*clear sub interrup status*/
        type.low_intr = INVG;
        CTC_ERROR_RETURN(_sys_usw_interrupt_clear_status_normal(lchip, &type, sub_bmp));
    }

    return CTC_E_NONE;
}

int32
sys_at_interrupt_init_reg(uint8 lchip)
{
    sys_intr_group_t* p_group = NULL;
    ds_t map_ctl;
    SupIntrGenCtl_m gen_ctl;
    uint32 cmd = 0;
    uint32 i = 0;
    uint32 j = 0;
    uint32 mask_set = 0;
    uint32 unmask_set = 0;
    uint32 value_set[2] = {0};
    uint8 step = 0;
    sys_intr_type_t type;
    uint32 value[CTC_INTR_STAT_SIZE] = {0};
    PcieIntfInterruptNormal_m pcie_normal;
    NetTxInterruptNormal_m    nettx_normal;
    QuadSgmacInterruptNormal0_m quadsgmac_normal;
    IpeAclInterruptNormal_m ipe_acl_normal;
    ds_t ds;
    uint32 intr_bmp[SYS_INTR_MAX_BMP_NUM] = {0};
    uint8 index = 0;
    uint8 oper_bmp = 0x40;/* MapCtl only need to consider Core 0 */
    uint16 intr_base = 0;
    uint32 table_id = 0;
    uint32 k = 0;
    
    sal_memset(map_ctl, 0, sizeof(map_ctl));
    sal_memset(&quadsgmac_normal, 0, sizeof(QuadSgmacInterruptNormal0_m));
    sal_memset(&gen_ctl, 0, sizeof(gen_ctl));

    mask_set = 0xFF;

    for (i = 0; i < SYS_USW_MAX_INTR_GROUP; i++)
    {
        p_group = &(p_usw_intr_master[lchip]->group[i]);
        if (p_group->group < 0)
        {
            continue;
        }

        if (p_group->group >= 0)
        {
            CTC_BIT_UNSET(mask_set, p_group->irq_idx);
        }

        switch (p_group->irq_idx)
        {
            case 0:
                table_id = SupIntrMap0Ctl_t;
                cmd = DRV_IOR(table_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, 0, ((uint64)oper_bmp << DRV_BITS_PER_WORD) | cmd, &map_ctl));
                GetSupIntrMap0Ctl(A, supIntrMap_f, &map_ctl, intr_bmp);
                for (index = 0; index < SYS_INTR_MAX_BMP_NUM; index++)
                {
                    intr_bmp[index] |= p_group->intr_bmp[index];
                }
                SetSupIntrMap0Ctl(A, supIntrMap_f, &map_ctl, intr_bmp);
                cmd = DRV_IOW(table_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, 0, ((uint64)oper_bmp << DRV_BITS_PER_WORD) | cmd, &map_ctl));
                break;

            case 1:
                table_id = SupIntrMap1Ctl_t;
                cmd = DRV_IOR(table_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, 0, ((uint64)oper_bmp << DRV_BITS_PER_WORD) | cmd, &map_ctl));
                GetSupIntrMap1Ctl(A, supIntrMap_f, &map_ctl, intr_bmp);
                for (index = 0; index < SYS_INTR_MAX_BMP_NUM; index++)
                {
                    intr_bmp[index] |= p_group->intr_bmp[index];
                }
                SetSupIntrMap1Ctl(A, supIntrMap_f, &map_ctl, intr_bmp);
                cmd = DRV_IOW(table_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, 0, ((uint64)oper_bmp << DRV_BITS_PER_WORD) | cmd, &map_ctl));
                break;

            case 2:
                table_id = SupIntrMap2Ctl_t;
                cmd = DRV_IOR(table_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, 0, ((uint64)oper_bmp << DRV_BITS_PER_WORD) | cmd, &map_ctl));
                GetSupIntrMap2Ctl(A, supIntrMap_f, &map_ctl, intr_bmp);
                for (index = 0; index < SYS_INTR_MAX_BMP_NUM; index++)
                {
                    intr_bmp[index] |= p_group->intr_bmp[index];
                }
                SetSupIntrMap2Ctl(A, supIntrMap_f, &map_ctl, intr_bmp);
                cmd = DRV_IOW(table_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, 0, ((uint64)oper_bmp << DRV_BITS_PER_WORD) | cmd, &map_ctl));
                break;

            case 3:
                table_id = SupIntrMap3Ctl_t;
                cmd = DRV_IOR(table_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, 0, ((uint64)oper_bmp << DRV_BITS_PER_WORD) | cmd, &map_ctl));
                GetSupIntrMap3Ctl(A, supIntrMap_f, &map_ctl, intr_bmp);
                for (index = 0; index < SYS_INTR_MAX_BMP_NUM; index++)
                {
                    intr_bmp[index] |= p_group->intr_bmp[index];
                }
                SetSupIntrMap3Ctl(A, supIntrMap_f, &map_ctl, intr_bmp);
                cmd = DRV_IOW(table_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, 0, ((uint64)oper_bmp << DRV_BITS_PER_WORD) | cmd, &map_ctl));
                break;

            default:
                break;
        }
    }

    unmask_set = (~mask_set)&0xff;

    cmd = DRV_IOW(SupIntrGenCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &mask_set));

    cmd = DRV_IOW(SupIntrGenCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &unmask_set));

    /* release fatal interrupt mask */
    for (i = 0; i < p_usw_intr_master[lchip]->fatal_sub_cnt; i++)
    {
        intr_base = p_usw_intr_master[lchip]->fatal_sub_base[i];
        for (j = 0; j < p_usw_intr_master[lchip]->p_intr_low_fatal[i].array_size; j++)
        {
            for (k = 0; k < p_usw_intr_master[lchip]->p_intr_fatal_end_tbl[j+intr_base].array_size; k++)
            {
                type.intr = SYS_INTR_CHIP_FATAL;
                type.sub_intr = i;
                type.low_intr = j;
                type.lvl4_intr = k;
                sys_at_interrupt_release_fatal(lchip, &type, 1);
            }
        }

    }

    /* release normal interrupt mask */
    for (i = 0; i < p_usw_intr_master[lchip]->normal_sub_cnt; i++)
    {
        intr_base = p_usw_intr_master[lchip]->normal_sub_base[i];
        for (j = 0; j < p_usw_intr_master[lchip]->p_intr_low_normal[i].array_size; j++)
        {
            for (k = 0; k < p_usw_intr_master[lchip]->p_intr_normal_end_tbl[j+intr_base].array_size; k++)
            {
                type.intr = SYS_INTR_CHIP_NORMAL;
                type.sub_intr = i;
                type.low_intr = j;
                type.lvl4_intr = k;
                sys_at_interrupt_release_normal(lchip, &type, 1);
            }
        }
    }
    
    cmd = DRV_IOR(DmaCtlInterruptFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);
    cmd = DRV_IOW(DmaCtlInterruptFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, value);

    cmd = DRV_IOR(I2CMasterInterruptNormal0_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);
    cmd = DRV_IOW(I2CMasterInterruptNormal0_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, value);

    cmd = DRV_IOR(I2CMasterInterruptNormal1_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);
    cmd = DRV_IOW(I2CMasterInterruptNormal1_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, value);

    cmd = DRV_IOR(CpuMapInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);
    cmd = DRV_IOW(CpuMapInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, value);

    cmd = DRV_IOR(PcieIntfInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);
    cmd = DRV_IOW(PcieIntfInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, value);

    cmd = DRV_IOR(DmaCtlInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);
    cmd = DRV_IOW(DmaCtlInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, value);

    value[0] = 0x847C3006;
    value[1] = 0x0000000F;
    cmd = DRV_IOW(DmaCtlInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);

    /* release function interrupt mask*/
    cmd = DRV_IOR(DmaCtlIntrFunc0_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value_set);
    cmd = DRV_IOW(DmaCtlIntrFunc0_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &value_set);
    /* mask unused dma function interrupt: dmaUserRegDone0, pktRx0...7DescEmptyIntr0, dmaInfo0...7DescEmptyIntr0*/
    value_set[0] = 0x80000000;
    value_set[1] = 0xffffffff;
    cmd = DRV_IOW(DmaCtlIntrFunc0_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value_set);
#if 0
    /* release function cpumac mask*/
    cmd = DRV_IOR(CpuMacProcInterruptFunc_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &ds);
    cmd = DRV_IOW(CpuMacProcInterruptFunc_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &ds);

    cmd = DRV_IOR(CpuMacProcInterruptFunc1_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &ds);
    cmd = DRV_IOW(CpuMacProcInterruptFunc1_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &ds);
#endif
    for(i = 0; i < 40; i++)
    {
        sal_memset(value, 0, sizeof(value));
        SetCtcHsCtlInterruptFunc(V, funcIntrHataTxTsToCpuFifo_f, value, 1);
        cmd = DRV_IOW(CtcHsCtlInterruptFunc_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET + (i * INTR_INDEX_MAX), cmd, &value);

        /* intrRxLocalDegraded/intrRxRemoteDegraded/intrRxFecDegraded */
        sal_memset(&ds, 0, sizeof(ds_t));
        ds[0] = 0x7f8ff;
        cmd = DRV_IOW(McPcs400InterruptNormal_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, DRV_INS(i, INTR_INDEX_MASK_SET), cmd, &ds);

        /* intrTxAsyncFifoUnderrunLane0Mcu */
        sal_memset(&ds, 0, sizeof(ds_t));
        ds[0] = 0x3ffc0;
        cmd = DRV_IOW(CtcHsCtlInterruptNormal_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, DRV_INS(i, INTR_INDEX_MASK_SET), cmd, &ds);

        /* intrTxAsyncFifoUnderrunLane0Mcu */
        sal_memset(&ds, 0, sizeof(ds_t));
        ds[0] = 0x3ffc0;
        cmd = DRV_IOW(CtcHsCtlInterruptNormal1_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, DRV_INS(i, INTR_INDEX_MASK_SET), cmd, &ds);
    }

    sal_memset(&ds, 0, sizeof(ds_t));
    /*anRemoteAnegErr/anRemoteLinkFailure/anRemoteOffline*/
    ds[0] = 0x0000FFF0;
    cmd = DRV_IOW(SharedPcsInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &ds);

    sal_memset(&ds, 0, sizeof(ds_t));
    /*intRxLintFault/intRxRemoteFault/intRxLocalFault/intRxLinkFault*/
    ds[0] = 0x0000FFFF;
    cmd = DRV_IOW(SharedMiiInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &ds);

    /* Not release PcieIntfInterruptFunc[10:5] */
    cmd = DRV_IOR(PcieIntfInterruptFunc_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value_set);
    value_set[0] = 0xFFFFF81F;
    cmd = DRV_IOW(PcieIntfInterruptFunc_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &value_set);

    sal_memset(&nettx_normal, 0, sizeof(NetTxInterruptNormal_m));
    SetNetTxInterruptNormal(V, rxNoEopErrorIntr0_f, &nettx_normal, 1);
    SetNetTxInterruptNormal(V, rxNoEopErrorIntr1_f, &nettx_normal, 1);
    SetNetTxInterruptNormal(V, rxNoEopErrorIntr2_f, &nettx_normal, 1);
    SetNetTxInterruptNormal(V, rxNoEopErrorIntr3_f, &nettx_normal, 1);
    SetNetTxInterruptNormal(V, rxNoSopErrorIntr0_f, &nettx_normal, 1);
    SetNetTxInterruptNormal(V, rxNoSopErrorIntr1_f, &nettx_normal, 1);
    SetNetTxInterruptNormal(V, rxNoSopErrorIntr2_f, &nettx_normal, 1);
    SetNetTxInterruptNormal(V, rxNoSopErrorIntr3_f, &nettx_normal, 1);
    cmd = DRV_IOW(NetTxInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &nettx_normal);

    cmd = DRV_IOR(PcieIntfInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &pcie_normal);
    SetPcieIntfInterruptNormal(V, hssRxAEyeQualityIntr_f, &pcie_normal, 1);
    SetPcieIntfInterruptNormal(V, hssRxBEyeQualityIntr_f, &pcie_normal, 1);
    SetPcieIntfInterruptNormal(V, pciePhyMemLaneUbe_f, &pcie_normal, 0xf);
    SetPcieIntfInterruptNormal(V, pciePhyMemCmnUbe_f, &pcie_normal, 0x1);
    SetPcieIntfInterruptNormal(V, testOutPcieIntr_f, &pcie_normal, 0x1);
    SetPcieIntfInterruptNormal(V, pcieTlpErrIntr_f, &pcie_normal, 0x1);
    SetPcieIntfInterruptNormal(V, testBridgeRxBufUeIntr_f, &pcie_normal, 0x1);
    cmd = DRV_IOW(PcieIntfInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &pcie_normal);

    /*mask IpeAclInterruptNormal.timestampOverrun*/
     cmd = DRV_IOR(IpeAclInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &ipe_acl_normal);
    SetIpeAclInterruptNormal(V, timestampOverrun_f, &ipe_acl_normal, 1);
    cmd = DRV_IOW(IpeAclInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &ipe_acl_normal);

    cmd = DRV_IOR(LinkAggInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value);
    SetLinkAggInterruptNormal(V, refChanAvgLoadOverlap_f, &value, 1);
    SetLinkAggInterruptNormal(V, refChanAvgQSizeOverlap_f, &value, 1);
    SetLinkAggInterruptNormal(V, refFlowSetActiveUpdateOverlap_f, &value, 1);
    SetLinkAggInterruptNormal(V, asyncCrossCoreOutputFifoDepthExceed_f, &value, 1);
    SetLinkAggInterruptNormal(V, other0LinkAggLoadQualityOverlap_f, &value, 1);
    SetLinkAggInterruptNormal(V, other1LinkAggLoadQualityOverlap_f, &value, 1);
    SetLinkAggInterruptNormal(V, other2LinkAggLoadQualityOverlap_f, &value, 1);
    SetLinkAggInterruptNormal(V, epeLinkAggLoadQualityOverlap_f, &value, 1);
    SetLinkAggInterruptNormal(V, asyncCrossCoreInputFifoDepthExceed_f, &value, 1);
    cmd = DRV_IOW(LinkAggInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value);

    cmd = DRV_IOR(SvcPolicingInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value);
    SetSvcPolicingInterruptNormal(V, scanOverlapIntr_f, &value, 1);
    cmd = DRV_IOW(SvcPolicingInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value);

    cmd = DRV_IOR(CtcMiscCtlInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value);
    SetCtcMiscCtlInterruptNormal(V, hMacEngineInterruptNormal_f, &value, 1);
    cmd = DRV_IOW(CtcMiscCtlInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value);

    sal_memset(value, 0, sizeof(value));
    SetQuadSgmacInterruptNormal(V, intSgmac0RxPauseLockDetect_f, &value, 1);
    SetQuadSgmacInterruptNormal(V, intSgmac1RxPauseLockDetect_f, &value, 1);
    SetQuadSgmacInterruptNormal(V, intSgmac2RxPauseLockDetect_f, &value, 1);
    SetQuadSgmacInterruptNormal(V, intSgmac3RxPauseLockDetect_f, &value, 1);
    cmd = DRV_IOW(QuadSgmacInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &value);


    sal_memset(value, 0xff, sizeof(value));
    cmd = DRV_IOW(InterruptVecXSecFunc_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &value);

    sal_memset(value, 0xff, sizeof(value));
    cmd = DRV_IOW(InterruptVecIpfixIpeOverflow_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &value);

    sal_memset(value, 0xff, sizeof(value));
    cmd = DRV_IOW(InterruptVecIpfixEpeOverflow_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &value);

    sal_memset(value, 0, sizeof(value));
    SetCpuMacProcInterruptNormal(V, quadSgmacInterruptNormal_f, &value, 1);
    cmd = DRV_IOW(CpuMacProcInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &value);

    sal_memset(value, 0, sizeof(value));
    SetCtcMiscCtlInterruptNormal(V, cpuMacProcInterruptNormal_f, &value, 1);
    cmd = DRV_IOW(CtcMiscCtlInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &value);

    cmd = DRV_IOR(MapIntrVecFuncLocal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &ds);
    /*mask pcie burst done*/
    ds[0] &= 0xFFFFBFFF;
    cmd = DRV_IOW(MapIntrVecFuncLocal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &ds);

    /* clear mask pfc normal interrupt*/
    step = QuadSgmacInterruptNormal0_intSgmac1RxPauseLockDetect_f - QuadSgmacInterruptNormal0_intSgmac0RxPauseLockDetect_f;
    for(i = 0; i <= 15; i++)
    {
        for(j = 0; j <= 3; j++)
        {
            SetQuadSgmacInterruptNormal0(V, intSgmac0RxPauseLockDetect_f+j*step, &quadsgmac_normal, 1);
        }
        cmd = DRV_IOW(QuadSgmacInterruptNormal0_t + i, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &quadsgmac_normal);
    }

    /*clear some interrupt */
    cmd = DRV_IOR(PcieIntfInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, 0, cmd, &value_set);
    cmd = DRV_IOW(PcieIntfInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, 1, cmd, &value_set);

    cmd = DRV_IOR(LinkAggInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_VAL_SET, cmd, &value);
    cmd = DRV_IOW(LinkAggInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_VAL_RESET, cmd, &value);

    cmd = DRV_IOR(CtcIpeTxCtlInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_VAL_SET, cmd, &value);
    cmd = DRV_IOW(CtcIpeTxCtlInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_VAL_RESET, cmd, &value);

    return CTC_E_NONE;
}


int32
sys_at_interrupt_set_sup_op(uint8 lchip, uint8 grp_id, uint8 act_idx)
{
    uint32 cmd = 0;
    SupIntrGenCtl_m sup_ctl;
    uint32 value = 0;

    value = (1 << grp_id);

    sal_memset(&sup_ctl, 0, sizeof(sup_ctl));

    SetSupIntrGenCtl(V, supIntrGen_f, &sup_ctl, value);

    /*When release msi interrup, clear PcieIntrLogCtl_pcieIntrLogVec_f*/
    if ((INTR_INDEX_MASK_RESET == act_idx) && (p_usw_intr_master[lchip]->intr_mode == CTC_INTR_MODE_MSI || p_usw_intr_master[lchip]->intr_mode == CTC_INTR_MODE_MSIX))
    {
        cmd = DRV_IOR(PcieIntrLogCtl_t, PcieIntrLogCtl_pcieIntrLogVec_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        CTC_BIT_UNSET(value, grp_id);
        cmd = DRV_IOW(PcieIntrLogCtl_t, PcieIntrLogCtl_pcieIntrLogVec_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    }

    cmd = DRV_IOW(SupIntrGenCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, act_idx, cmd, &sup_ctl));
    
    return CTC_E_NONE;
}

#endif
